In microprocessors of recent years, a high-speed cache memory with low storage capacity composed of, for example, a Static Random Access Memory (SRAM), has been installed within or near the microprocessor, and by storing a part of data in the cache memory, memory access speed of the microprocessor is increased.
Various techniques which aim to increase cache efficiency (to enhance a hit ratio and reduce cache miss latency) are known conventionally. One of such techniques is preloading (or prefetching), by which data to be used in the near future is filled in advance into the cache before a cache miss occurs (for example, Patent Reference 1). This technique can reduce cache misses by loading a line that includes a designated address into the cache by a prefetch instruction.
Patent Reference 1: Japanese Unexamined Patent Application No. 7-295882